Reference Models for RISC-V Processor Verification and Software Development

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The open standard ISA of RISC-V gives new degrees of design freedom to system designers, software developers and processor hardware implementers. Supporting the ISA specification is the growing ecosystem of partners that provide the essential infrastructure that developers can rely on from project inception to production. Today’s talks will be with Simon Davidmann from Imperas, and will cover adaptable verification methods that complement the design innovations of RISC-V, plus the use of virtual platforms for software development and architectural exploration with RISC-V custom instructions.

About the Speaker

Simon Davidmann
Founder and CEO
Imperas

Simon Davidmann is founder and CEO of Imperas and initiator of Open Virtual Platforms. Prior to founding Imperas, Simon was a VP in Synopsys following its successful acquisition of Co-Design Automation, the developer of SystemVerilog. Prior to founding Co-Design Automation, Simon was an executive or European GM with 5 US-based EDA startups including Chronologic Simulation, which pioneered the compiled code simulator VCS, and Ambit. Simon was one of the original developers of the HILO logic simulation system, and co-authored the definitive book on SystemVerilog.

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Module Includes

  • 6 Sections

Prize Giveaways

We are giving away more than $3,500 in prizes to 14 lucky attendees.