Launched in 2010, the RISC-V instruction set architecture (ISA) is provided under open-source licenses that do not require fees to use. The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International Technical Working Groups. The RISC-V ecosystem is continuously expanding, with tools and design resources developed by numerous third parties that support RISC-V based designs.
Being an open-source technology, verification and certification are important to ensure that the developed solutions are compatible with existing devices in the ecosystem, and enable the effective reuse of community IP. In addition, the next generation of processor engineers need to be educated in the latest RISC-V development tools and workload-targeted chip design. The open RISC-V architecture is empowering a generation of development by giving everyone, regardless of size, an opportunity to compete.
This webinar will explore how chip design will be enabled by the RISC-V ecosystem, and how it can enable industry-wide collaboration to build solutions based on a common set of standards and specifications.
- Software development
- Hardware development
- verification and certification
Course Includes
- 3 Lessons
